DFT–BIST FRAMEWORK FOR ENHANCING SECURITY AND RELIABILITY OF VLSI SYSTEMS IN HYBRID MODE

Abstract

Reliability degradation, test complexity and emerging hardware security issues like hardware Trojans and side channel attacks are increasingly becoming a challenge for modern Very Large-Scale Integration (VLSI) systems. The conventional Design-for-Testability (DFT) techniques such as scan testing, and Built-In Self-Test (BIST) architectures have each performed a contribution to facilitate increased fault coverage and in-field self-test capability. But they sometimes lack flexibility in supporting intelligent fault behaviors, security precautions because of scan chain exposure, and test overhead due to increased test length. To overcome these issues, a Hybrid DFT–BIST framework is suggested which combines scan-based controllability with adaptive BIST mechanisms and security aware monitoring strategies. The proposed architecture uses light weight signature compaction, pseudo random test pattern generation, on chip and machine learning based anomaly detection to improve both reliability and security of the VLSI systems. Hybrid integration results in more accurate fault detection, quicker test application time, and stronger resistance to malicious hardware changes. The proposed framework is shown to be superior to the conventional standalone DFT and BIST methods in terms of fault coverage, test efficiency and security robustness when using the comparative analysis. The study also highlights the need for co-design of the testability and security requirements of next-generation System-on-Chip (SoC) architectures.