IMPLEMENTATION OF BIST ARCHITECTURE FOR LOW-POWER AND SECURE VLSI CIRCUITS

Abstract

As Very Large-Scale Integration (VLSI) systems are rapidly scaling, efficient testing, power consumption and hardware security has become increasingly challenging. one of the most popular Design-for-Testability (DFT) approaches is the Built-In Self-Test (BIST) architecture, because of the capability of having on-chip testing with low dependence on external testing equipment. But the conventional BIST approaches usually require high switching activity, high power consumption in test mode, and possible security issues including scan-based side-channel attack and IP piracy. In this paper, an integrated approach for implementation of low-power, secure BIST architecture with advanced techniques like power-aware test pattern generation, scan chain obfuscation, Physically Unclonable Functions (PUFs) and lightweight cryptographic control logic is proposed. The proposed framework provides better fault coverage and reduces the dynamic and leakage power during test, and increases the resistance against hardware attacks. A summary of recent achievements (2020–2026) is completed to provide an overview of novel directions of secure and energy-efficient BIST design.