MACHINE LEARNING-BASED FAULT PREDICTION IN VLSI CIRCUITS USING DFT TEST DATA

Abstract

The scaling of Very Large-Scale Integration (VLSI) circuits into more complex designs has made fault modeling, detection and diagnosis more complicated. Conventional Design for Testability (DFT) techniques, such as scan-based testing, Built-In Self-Test (BIST) and Automatic Test Pattern Generation (ATPG), have proved very effective, but are becoming more costly and time intensive to implement in advanced nodes. Recently Machine Learning (ML) techniques have been emerging as a very promising approach to improving the accuracy of the fault prediction, learning patterns from the test data generated by DFT. This paper proposes an extensive approach to combine ML models and DFT tests to predict the circuit level faults efficiently. The proposed approach utilizes features derived from the scan chain output, ATPG vectors and fault simulation responses for supervised learning models like Random Forest, Support Vector Machines, and deep neural networks. Recent literature has shown that ML-based methods can achieve fault detection accuracy over 95% with a great reduction in test pattern generation time and computational complexity. The role of data imbalance, feature extraction constraints in large-scale SoC designs and scalability issues are also discussed briefly in the study.