High-Speed MAC Unit Design using Sequential Finite-Field Multiplier and Pipelined Adder Architecture for DSP Applications

Abstract

In the realm of digital signal processors (DSPs), there is always a demand for additional processing capacity, particularly when it comes to the incorporation of a greater number of central processing unit cores onto a single integrated circuit. Digital signal processors (DSPs) are capable of performing a wide variety of operations, including convolution, transformation, correlation, and filtering, which essentially need multiplication and repeated addition. The Multiply and Accumulate unit (MAC) is an essential component of digital signal processors (DSPs), which highlights the importance of implementing high-performance operations inside this unit. There is a major dependence on the speed performance of the MAC for DSP algorithms. The implementation of MAC architecture has traditionally been accomplished through the use of bit-parallel computing techniques. However, as bit precision grows, these techniques result in quadratic increases in the amount of hardware that is required. Alternatively, bit-serial computing is a method that serializes a single input in order to make hardware proportionate to bit precision. It reduces the requirements for hardware. Another significant challenge that arises as technology progresses is the dissipation of static power. Based on the Sequential Finite-Field Multiplier (SFFM) methodology, this research provides a high-speed MAC unit that was developed specifically for use in arithmetic applications. When designing the adder blocks that are contained within the MAC unit, the high-speed pipelined adder architecture is something that is utilized.