POWER EFFICIENT DESIGN OF ADIABATIC APPROACH FOR LOW POWER VLSI CIRCUIT

Abstract

In the current situation, low power VLSI circuits are produced by minimising power consumption in electronic circuits via the use of the adiabatic technique. For low power consumption, adiabatic logic circuits come in a variety of forms. This article proposes a comparison of the power consumption of adiabatic logic utilising Positive Feedback Adiabatic Logic (PFAL) and Two Phase Adiabatic Static Clocked logic (2PASCL). Flip flops are the primary parts in digital design that are in charge of storing in every SOC