DRIP CURRENT: MOORE’S LAW MEETS STANDING POWER

Abstract

With technological down scaling, static power has become one of the main issues in a system on chip. One intriguing approach to overcoming this difficulty is the use of normally off computing with non-volatile (NV) sequential components. In general, many distinct designs for NV shadow flip-flops have been presented, with magnetic tunnel junction (MTJ) cells serving as redundant data storage mechanisms. Compared to its CMOS counterparts, MTJs are more prone to manufacturing faults because of the evolving fabrication procedures of magnetic layers. In addition, memory arrays are easily repairable because to well-established memory repair and coding systems, but flip-flops dispersed throughout the layout are more challenging to repair. As a result, NV flip-flops need robust defect and fault tolerance to provide a high production yield. In this research, we present a design for a fault-tolerant NV latch (FTNV-L) that is resistant to several types of MTJ cell failures. All single MTJ faults may be tolerated by our suggested FTNV-L with far less overhead than with conventional methods, as shown by our simulation findings. This sram design with FF implementation project has been extended to us.