Design and Implementation of High-Speed Vedic Multiplier Architectures Using Optimized Adder Topologies for Efficient VLSI Systems

Abstract

The evolution of VLSI design has heightened the need for high-speed, low-power, and area efficient arithmetic units. Among these, multipliers are fundamental components in digital signal processing (DSP), microprocessors, and various computation-intensive applications. This paper presents the design and implementation of Vedic multipliers, leveraging ancient Indian mathematics to develop fast, power-efficient multipliers using Ripple Carry Adders (RCA), Carry Select Adders (CSelA), CSelA with Binary to Excess-1 Code (BEC), and CSelA with Common Boolean Logic (CBL). Simulation and synthesis are performed using Cadence tools, showcasing significant improvements in speed, area, and power consumption compared to conventional designs.