DESIGN AND IMPLEMENTATION OF HIGH PERFORMANCE, LOW POWER MASKED 128-AES USING FPGA. International Journal of Food and Nutritional Sciences, [S. l.], v. 11, n. 11, p. 17998–18004, 2022. Disponível em: https://www.ijfans.org/index.php/Journal/article/view/12438. Acesso em: 18 jul. 2026.